In a typical semiconductor device, a nominal n-well is used to sustain high voltage as part of a standard CMOS process for tunneling transistors or coupling capacitors. Such high voltage components may be implemented in charge pump circuits, high voltage switch circuits, and the like.
Furthermore, a high voltage n-well which can sustain a voltage as high as 20V may be needed for a memory device with 5V I/O oxide developed in a standard CMOS process without extra masks for high voltage circuits and components (e.g. charge pumps, high voltage switches, tunneling transistors, LDMOS). However, the breakdown voltage of the n-well is usually determined by the I/O or logic device and decreases with more advanced technology.
A high voltage n-well, which can sustain a voltage as high as 12V, may be needed for a memory device (e.g. Non-Volatile Memory) with 3.3V I/O oxide developed in a standard CMOS process without extra masks for high voltage circuits and components. However, the breakdown of the n-well decreases with more advanced technology implementing thinner layers (0.18 micron MFS, 0.13 micron MFS, 0.09 micron MFS, etc.). For example, a 0.13 micron MFS device has an n-well breakdown voltage of 10V.
As device geometries and minimum feature sizes (MFS) shrink, e.g., from 0.18 micron MFS to 0.13 micron MFS to 0.09 micron MFS and beyond, new ways to provide relatively high breakdown voltages, particularly in logic CMOS processes, become more and more important. Logic CMOS is important because it is commonly available at low cost with minimum process steps.